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Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

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Title Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics
 
Creator CHANDORKAR, AN
BORSE, DG
VAIDYA, SJ
 
Subject mos capacitors
mos integrated circuits
vlsi
annealing
dielectric thin films
electron traps
integrated circuit measurement
integrated circuit reliability
leakage currents
 
Description Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied.
 
Publisher IEEE
 
Date 2008-11-21T06:59:27Z
2011-11-25T12:42:18Z
2011-12-26T13:08:52Z
2011-12-27T05:34:15Z
2008-11-21T06:59:27Z
2011-11-25T12:42:18Z
2011-12-26T13:08:52Z
2011-12-27T05:34:15Z
2002
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 49 (4), 699-701
0018-9383
http://dx.doi.org/10.1109/16.992883
http://hdl.handle.net/10054/86
http://dspace.library.iitb.ac.in/xmlui/handle/10054/86
 
Language en_US