Record Details

Using soft secondary electron programming to reduce drain disturb in floating-gate nor flash EEPROMs

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Using soft secondary electron programming to reduce drain disturb in floating-gate nor flash EEPROMs
 
Creator MAHAPATRA, S
BHARATH KUMAR, P
NAIR, DR
 
Subject computer programming
electron tunneling
rom
 
Description A novel concept of soft secondary electron programming (SSEP) is introduced and shown to be a promising programming scheme for scaled NOR flash electrically erasable programmable read-only memories. Although the mechanism is similar to that of the channel-initiated secondary electron (CHISEL) programming, SSEP uses an "optimum" substrate bias that results in a lower drain disturb compared with both channel hot electron (CHE) and conventional CHISEL programming schemes. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, as well as better program/disturb margin compared with conventional CHISEL programming at similar program speed or disturb time. The effect of repeated program/erase cycling using SSEP is compared against CHE and CHISEL cycling.
 
Publisher IEEE
 
Date 2008-11-25T05:57:31Z
2011-11-25T12:44:18Z
2011-12-26T13:08:54Z
2011-12-27T05:34:18Z
2008-11-25T05:57:31Z
2011-11-25T12:44:18Z
2011-12-26T13:08:54Z
2011-12-27T05:34:18Z
2006
 
Type Article
 
Identifier IEEE Transactions on Device and Materials Reliability 6(1), 81-86
1530-4388
http://dx.doi.org/10.1109/TDMR.2006.871149
http://hdl.handle.net/10054/139
http://dspace.library.iitb.ac.in/xmlui/handle/10054/139
 
Language en_US