Record Details

Generation of high power test vector set for combinational VLSI circuits

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Generation of high power test vector set for combinational VLSI circuits
 
Creator THARAKAN, KTO
RAO, SSSP
 
Subject burn-in simulation
latent defects
failure mechanisms
burn-in test vectors
stress testing
vlsi devices
vlsi circuits
cmos signal switching
power vectors
algorithm
cmos gates
cmos device
complementary metal oxide semiconductor device
 
Description Burn-in is a well-known technique that helps to accelerate failure mechanisms to surface out latent defects, which are not activated during normal testing of the VLSI devices. The devices are kept at a specified high temperature, for a specified period, in static or dynamic conditions. Since this method is cumbersome, an alternate method based on complementary metal oxide semiconductor (CMOS) signal switching for VLSI devices is,considered. The majority of power dissipation in CMOS circuitry is due to the switching current associated with charging and discharging of load capacitances. Hence, if the test vectors can be so designed that maximum activity is conjured, the stress on the device can be maximised. In this paper, a new algorithm for generation of these power vectors from a gate-level description of the circuit is presented. The method has been applied to different circuits and the results compared.
 
Publisher DEFENCE SCIENTIFIC INFORMATION DOCUMENTATION CENTRE
 
Date 2011-07-21T08:25:27Z
2011-12-26T12:51:58Z
2011-12-27T05:38:49Z
2011-07-21T08:25:27Z
2011-12-26T12:51:58Z
2011-12-27T05:38:49Z
2002
 
Type Article
 
Identifier DEFENCE SCIENCE JOURNAL, 52(4), 351-356
0011-748X
http://dspace.library.iitb.ac.in/xmlui/handle/10054/5847
http://hdl.handle.net/10054/5847
 
Language en