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Parasitic effects in multi-gate MOSFETs

DSpace at IIT Bombay

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Title Parasitic effects in multi-gate MOSFETs
 
Creator KOBAYASHI, Y
MANOJ, CR
TSUTSUI, K
HARIHARAN, V
KAKUSHIMA, K
RAO, VR
AHMET, P
IWAI, H
 
Subject finfet
multi-gate
fin-fets
high-k dielectric
fringe capacitance
parasitic effect
 
Description In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.
 
Publisher IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
 
Date 2011-08-01T20:11:04Z
2011-12-26T12:53:29Z
2011-12-27T05:39:35Z
2011-08-01T20:11:04Z
2011-12-26T12:53:29Z
2011-12-27T05:39:35Z
2007
 
Type Article
 
Identifier IEICE TRANSACTIONS ON ELECTRONICS, E90C(10), 2051-2056
0916-8524
http://dx.doi.org/10.1093/ietele/e90-c.10.2051
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8532
http://hdl.handle.net/10054/8532
 
Language en