Record Details

Optimised weighted-resistor digital to analogue converter

DSpace at IIT Bombay

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Field Value
 
Title Optimised weighted-resistor digital to analogue converter
 
Creator RATHORE, TS
 
Subject weighted resistor
digital to analogue converter
 
Description From the classical weighted-resistor (WR) digital to analogue converter (DAC), two-stage DACs are derived. Conditions for minimum spread and the minimum total resistance for the two-stage DACs are derived. The theory is extended to multistage WR DACs. Thus, an optimised WR DAC is obtained that has minimum spread and the minimum total resistance and is therefore, suitable for economic fabrication in integrated circuit form.
 
Publisher IEE-INST ELEC ENG
 
Date 2011-07-31T11:05:49Z
2011-12-26T12:52:59Z
2011-12-27T05:40:01Z
2011-07-31T11:05:49Z
2011-12-26T12:52:59Z
2011-12-27T05:40:01Z
1998
 
Type Article
 
Identifier IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 145(3), 197-200
1350-2409
http://dx.doi.org/10.1049/ip-cds:19981814
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8094
http://hdl.handle.net/10054/8094
 
Language en