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Window-based cell scheduling algorithm for VLSI implementation of an input-queued ATM switch

DSpace at IIT Bombay

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Title Window-based cell scheduling algorithm for VLSI implementation of an input-queued ATM switch
 
Creator SANTHANAM, A
KARANDIKAR, A
 
Subject packet switch
 
Description A method for providing bandwidth reservations in an input-buffered self-routing crossbar switch architecture is introduced and analysed. The scheme computes a conflict-free set of flows within a cell slot and achieves a link utilisation as high as 93% for uniform random bursty traffic. Simulations of the proposed algorithm have been performed for different window sizes (W = 1, 2, 4, 8) and the cell loss probability (CLP), cell waiting time (CWT) and system throughput (ST) are estimated. The VLSI implementation of the scheme is also described.
 
Publisher IEE-INST ELEC ENG
 
Date 2011-07-31T12:25:55Z
2011-12-26T12:53:01Z
2011-12-27T05:40:05Z
2011-07-31T12:25:55Z
2011-12-26T12:53:01Z
2011-12-27T05:40:05Z
2000
 
Type Article
 
Identifier IEE PROCEEDINGS-COMMUNICATIONS, 147(2), 119-122
1350-2425
http://dx.doi.org/10.1049/ip-com:20000147
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8119
http://hdl.handle.net/10054/8119
 
Language en