Record Details

A Novel Table-Based Approach for Design of FinFET Circuits

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title A Novel Table-Based Approach for Design of FinFET Circuits
 
Creator THAKKER, RA
SATHE, C
SACHID, AB
BAGHINI, MS
RAO, VR
PATIL, MB
 
Subject particle swarm optimization
mosfet model
simulation
device
performance
transistor
splines
impact
gate
circuit design
finfet
hierarchical particle swarm optimization (pso)
lookup table (lut)
 
Description A new lookup-table (LUT) approach, based on normalization of the drain current with an I(D)-V(G) template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-07-31T18:36:52Z
2011-12-26T12:53:06Z
2011-12-27T05:40:14Z
2011-07-31T18:36:52Z
2011-12-26T12:53:06Z
2011-12-27T05:40:14Z
2009
 
Type Article
 
Identifier IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(7), 1061-1070
0278-0070
http://dx.doi.org/10.1109/TCAD.2009.2017431
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8198
http://hdl.handle.net/10054/8198
 
Language en