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Assessment of SET logic robustness through noise margin modeling

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Title Assessment of SET logic robustness through noise margin modeling
 
Creator SATHE, C
DAN, SS
MAHAPATRA, S
 
Subject single-electron transistor
circuits
devices
simulator
design
background charge
compact model
coulomb blockade
noise margin (nm)
single-electron transistor (set)
 
Description A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (C-G and C-T) It is shown that choosing alpha = C-T/C-G = 1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to +/- 0.03e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that alpha is an element of [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-07-31T21:25:28Z
2011-12-26T12:53:09Z
2011-12-27T05:40:20Z
2011-07-31T21:25:28Z
2011-12-26T12:53:09Z
2011-12-27T05:40:20Z
2008
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 55(3), 909-915
0018-9383
http://dx.doi.org/10.1109/TED.2007.915086
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8242
http://hdl.handle.net/10054/8242
 
Language en