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Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs

DSpace at IIT Bombay

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Title Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs
 
Creator KUMAR, DV
NARASIMHULU, K
REDDY, PS
SHOJAEI-BAGHINI, M
SHARMA, DK
PATIL, MB
RAO, VR
 
Subject model
profile
design
analog circuit
channel engineering
lateral asymmetric channel (lac)
look-up table (lut)
mosfet
quasi-static
 
Description Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-mu m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-08-01T02:51:25Z
2011-12-26T12:53:14Z
2011-12-27T05:40:29Z
2011-08-01T02:51:25Z
2011-12-26T12:53:14Z
2011-12-27T05:40:29Z
2005
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(7), 1603-1609
0018-9383
http://dx.doi.org/10.1109/TED.2005.850941
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8320
http://hdl.handle.net/10054/8320
 
Language en