Record Details

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation
 
Creator NAIR, DR
MAHAPATRA, S
SHUKURI, S
BUDE, JD
 
Subject enhanced gate current
technological parameters
vlsi mosfets
part ii
cells
memory
band-to-band tunneling (btbt)
channel hot electron (che)
device scaling
drain disturb
channel-initiated secondary electron (chisel)
flash eeproms
hot carriers
 
Description The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in. source/drain leakage, reduction in hand-to-hand tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-08-01T03:05:29Z
2011-12-26T12:53:14Z
2011-12-27T05:40:29Z
2011-08-01T03:05:29Z
2011-12-26T12:53:14Z
2011-12-27T05:40:29Z
2005
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(4), 534-540
0018-9383
http://dx.doi.org/10.1109/TED.2005.844741
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8323
http://hdl.handle.net/10054/8323
 
Language en