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Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization

DSpace at IIT Bombay

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Title Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization
 
Creator SACHID, AB
MANOJ, CR
SHARMA, DK
RAO, VR
 
Subject circuit performance
nanoscale finfets
dielectrics
mosfets
fibl
device
cmos scaling
finfet
fringe-induced barrier lowering (gfibl)
high-kappa materials
short-channel effects (sces)
 
Description The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I-on. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa = 20 spacers, we show that it is possible to achieve an 80% increase in I-on at iso-I-off conditions and a 15% decrease in the inverter delay for a fan-out of four.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-08-01T03:47:37Z
2011-12-26T12:53:15Z
2011-12-27T05:40:30Z
2011-08-01T03:47:37Z
2011-12-26T12:53:15Z
2011-12-27T05:40:30Z
2008
 
Type Article
 
Identifier IEEE ELECTRON DEVICE LETTERS, 29(1), 128-130
0741-3106
http://dx.doi.org/10.1109/LED.2007.911974
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8332
http://hdl.handle.net/10054/8332
 
Language en