Record Details

Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

DSpace at IIT Bombay

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Field Value
 
Title Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs
 
Creator MANOJ, CR
SACHID, AB
YUAN, F
CHANG, CY
RAO, VR
 
Subject double-gate
device
design
nm
epi thickness
finfets
fin pitch
fringe capacitance
junction capacitance
 
Description In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this increase is due to the 3-D nature of the device and also due to the close proximity of the source/drain (S/D) epitaxial (epi) region to the metal gate. Using well-calibrated 3-D mixed-mode simulations, we show that this will cause the performance of FinFETs to be significantly degraded, unless proper device optimizations are carried out. Our results also indicate that the selective epi growth of S/D may adversely affect the overall performance of FinFETs, although it is effective in reducing series resistance. The increased parasitic components in FinFETs can be a serious issue for FinFET circuits with a large fan-out, and the solution lies in the aggressive fin pitch reduction, as shown in this letter.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-08-01T04:46:39Z
2011-12-26T12:53:16Z
2011-12-27T05:40:32Z
2011-08-01T04:46:39Z
2011-12-26T12:53:16Z
2011-12-27T05:40:32Z
2010
 
Type Article
 
Identifier IEEE ELECTRON DEVICE LETTERS, 31(1), 83-85
0741-3106
http://dx.doi.org/10.1109/LED.2009.2035934
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8346
http://hdl.handle.net/10054/8346
 
Language en