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Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs

DSpace at IIT Bombay

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Title Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs
 
Creator MANOJ, CR
RAO, VR
 
Subject mosfets
nm
fin field-effect transistors (finfets)
fringing-induced barrier lowering (fibl)
high-k gate dielectric
noise margin
short-channel effects (sces)
 
Description The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C-of in addition to an increase in the internal fringe capacitance C-if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2011-08-01T04:55:05Z
2011-12-26T12:53:16Z
2011-12-27T05:40:32Z
2011-08-01T04:55:05Z
2011-12-26T12:53:16Z
2011-12-27T05:40:32Z
2007
 
Type Article
 
Identifier IEEE ELECTRON DEVICE LETTERS, 28(4), 295-297
0741-3106
http://dx.doi.org/10.1109/LED.2007.892365
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8348
http://hdl.handle.net/10054/8348
 
Language en