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A reordering algorithm for data compression for FPGA configurations

DSpace at IIT Bombay

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Title A reordering algorithm for data compression for FPGA configurations
 
Creator KUMAR, N
USHA, P
SOHONI, M
RAO, SSS
 
Description With the introduction of programmable logic devices with large capacities, the time taken to configure these devices has been of prime concern. One of the simplest solutions to reduce the configuration time is to compress the bit stream, as the compressed data would take lesser time to load on the device. Lossless compression can be achieved by using sophisticated algorithms but none of these algorithms have been able to achieve the theoretical limit to which the data can be compressed. This paper presents an algorithm for reordering the configuration bit stream prior to compression to improve upon the compression efficiency.
 
Publisher INST ELECTRONICS TELECOMMUNICATION ENGINEERS
 
Date 2011-08-03T04:53:02Z
2011-12-26T12:54:02Z
2011-12-27T05:41:20Z
2011-08-03T04:53:02Z
2011-12-26T12:54:02Z
2011-12-27T05:41:20Z
2001
 
Type Article
 
Identifier IETE TECHNICAL REVIEW, 18(5), 375-380
0255-9609
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8899
http://hdl.handle.net/10054/8899
 
Language en