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Modelling and simulation of multi-layered VLSI interconnects used in high-speed communications

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Title Modelling and simulation of multi-layered VLSI interconnects used in high-speed communications
 
Creator KULKARNI, SY
MURTHY, KVV
 
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Description The major problem in the design and implementation of very high speed communication systems using multichip modules (MCMs) is to control delay and losses in interconnects. Advances in the IC technology, especially, processing techniques have made it possible to develop ICs to operate at 100 to 150 picosecs. Even, the off-chip circuits can be designed to operate at this high speed. Signal lines are modelled as transmission lines with electrical representative parameters like [R], [L], [C] and [G] in PUL units. In this paper finite element technique has been employed to obtain these parameters. Special singular and infinite elements are used to improve upon the accuracy of the results. Modal analysis technique is applied to obtain time-domain response of these signal lines which are fabricated in multilayer multiconductor configurations. The trapezoidal and inverse trapezoidal cross-section conductors are common due to undercuts and epitaxial growth processes. Time-domain response of such conductors in multilayer structures is also analysed in this paper.
 
Publisher INST ELECTRONICS TELECOMMUNICATION ENGINEERS
 
Date 2011-08-03T06:08:55Z
2011-12-26T12:54:04Z
2011-12-27T05:41:24Z
2011-08-03T06:08:55Z
2011-12-26T12:54:04Z
2011-12-27T05:41:24Z
1998
 
Type Article
 
Identifier IETE TECHNICAL REVIEW, 15(1-2), 111-118
0256-4602
http://dspace.library.iitb.ac.in/xmlui/handle/10054/8921
http://hdl.handle.net/10054/8921
 
Language en