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A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells

DSpace at IIT Bombay

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Title A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells
 
Creator DATTA, A
MAHAPATRA, S
 
Subject memory cell
device
charge
impact
nrom
non-volatile semiconductor memory (nvsm)
sonos
2-bit operation
halo implant
compensation implant
bit coupling
read disturb
program speed
cell scaling
 
Description Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed. However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read VD. The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells. (C) 2009
 
Publisher PERGAMON-ELSEVIER SCIENCE LTD
 
Date 2011-08-23T04:59:35Z
2011-12-26T12:56:18Z
2011-12-27T05:44:46Z
2011-08-23T04:59:35Z
2011-12-26T12:56:18Z
2011-12-27T05:44:46Z
2010
 
Type Article
 
Identifier SOLID-STATE ELECTRONICS, 54(4), 397-404
0038-1101
http://dx.doi.org/10.1016/j.sse.2009.11.006
http://dspace.library.iitb.ac.in/xmlui/handle/10054/10398
http://hdl.handle.net/10054/10398
 
Language en