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Border-trap characterization in high-κ strained-Si MOSFETs

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Title Border-trap characterization in high-κ strained-Si MOSFETs
 
Creator MAJI, DEBABRATA
DUTTAGUPTA, SP
RAMGOPAL RAO, V
YEO, CHIA CHING
CHO, BYUNG-JIN
 
Subject drain current
gate dielectrics
hysteresis
semiconducting silicon
 
Description In this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si0.8Ge0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
 
Publisher IEEE
 
Date 2008-12-01T04:54:43Z
2011-11-25T16:01:45Z
2011-12-26T13:05:15Z
2011-12-27T05:51:32Z
2008-12-01T04:54:43Z
2011-11-25T16:01:45Z
2011-12-26T13:05:15Z
2011-12-27T05:51:32Z
2007
 
Type Article
 
Identifier IEEE Electron Device Letters 28(8), 731-33
0741-3106
http://dx.doi.org/10.1109/LED.2007.902086
http://hdl.handle.net/10054/200
http://dspace.library.iitb.ac.in/xmlui/handle/10054/200
 
Language en_US