SEU reliability analysis of advanced deep-submicron transistors
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
SEU reliability analysis of advanced deep-submicron transistors
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Creator |
VASI, J
JAIN, PALKESH LAL, RAKESH |
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Subject |
computer simulation
dielectric materials interfaces (materials) reliability |
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Description |
A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-κ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-κ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.
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Publisher |
IEEE
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Date |
2008-11-26T09:47:07Z
2011-11-25T16:02:45Z 2011-12-26T13:05:18Z 2011-12-27T05:51:44Z 2008-11-26T09:47:07Z 2011-11-25T16:02:45Z 2011-12-26T13:05:18Z 2011-12-27T05:51:44Z 2005 |
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Type |
Article
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Identifier |
IEEE Transactions on Device and Materials Reliability 5 (2), 289-95
1530-4388 http://dx.doi.org/10.1109/TDMR.2005.848325 http://hdl.handle.net/10054/185 http://dspace.library.iitb.ac.in/xmlui/handle/10054/185 |
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Language |
en_US
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