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A new method to characterize border traps in submicron transistors using hysteresis in the drain current

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Title A new method to characterize border traps in submicron transistors using hysteresis in the drain current
 
Creator RAMGOPAL RAO, V
MANJULA RANI, KN
VASI, J
 
Subject misfet
electron traps
semiconductor device measurement
transients
vapour deposition
 
Description In this paper, a new method for measuring border trap density (nBT) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which nBT is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.
 
Publisher IEEE
 
Date 2008-11-26T06:38:48Z
2011-11-25T12:24:14Z
2011-12-26T13:05:29Z
2011-12-27T05:52:33Z
2008-11-26T06:38:48Z
2011-11-25T12:24:14Z
2011-12-26T13:05:29Z
2011-12-27T05:52:33Z
2003
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 50(4), 973-79
0018-9383
http://dx.doi.org/10.1109/TED.2003.812101
http://hdl.handle.net/10054/150
http://dspace.library.iitb.ac.in/xmlui/handle/10054/150
 
Language en_US