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Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling

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Title Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling
 
Creator NAIR, DR
SHUKURI, S
MAHAPATRA, S
 
Subject nor circuits
flash memories
hot carriers
integrated circuit design
integrated circuit reliability
integrated circuit testing
logic design
 
Description The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 μm.
 
Publisher IEEE
 
Date 2009-01-02T04:10:51Z
2011-11-25T16:25:19Z
2011-12-26T13:05:30Z
2011-12-27T05:52:34Z
2009-01-02T04:10:51Z
2011-11-25T16:25:19Z
2011-12-26T13:05:30Z
2011-12-27T05:52:34Z
2004
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 51(10), 1672-1678
0018-9383
http://dx.doi.org/10.1109/TED.2004.835996
http://hdl.handle.net/10054/526
http://dspace.library.iitb.ac.in/xmlui/handle/10054/526
 
Language en