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Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

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Title Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation
 
Creator MAHAPATRA, S
NAIR, DR
SHUKURI, S
BUDE, JD
 
Subject computer simulation
electron tunneling
flash memory
monte carlo methods
 
Description The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
 
Publisher IEEE
 
Date 2008-11-24T05:23:39Z
2011-11-25T12:23:14Z
2011-12-26T13:05:44Z
2011-12-27T05:53:00Z
2008-11-24T05:23:39Z
2011-11-25T12:23:14Z
2011-12-26T13:05:44Z
2011-12-27T05:53:00Z
2005
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 54(4), 534-40
http://hdl.handle.net/10054/99
http://dspace.library.iitb.ac.in/xmlui/handle/10054/99
 
Language en_US