Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation
DSpace at IIT Bombay
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Title |
Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation
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Creator |
MAHAPATRA, S
NAIR, DR MOHAPATRA, NR SHUKURI, S BUDE, JD |
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Subject |
flash memories
integrated circuit design integrated memory circuits tunnelling |
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Description |
Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated program/erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower program/disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
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Publisher |
IEEE
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Date |
2008-11-24T05:27:50Z
2011-11-25T12:36:16Z 2011-12-26T13:06:12Z 2011-12-27T05:54:01Z 2008-11-24T05:27:50Z 2011-11-25T12:36:16Z 2011-12-26T13:06:12Z 2011-12-27T05:54:01Z 2004 |
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Type |
Article
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Identifier |
IEEE Transactions on Device and Materials Reliability 4(1), 32-37
1530-4388 http://dx.doi.org/10.1109/TDMR.2004.824371 http://hdl.handle.net/10054/105 http://dspace.library.iitb.ac.in/xmlui/handle/10054/105 |
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Language |
en_US
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