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Reconfigurable finite-state machine based IP lookup engine for high-speed router

DSpace at IIT Bombay

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Title Reconfigurable finite-state machine based IP lookup engine for high-speed router
 
Creator DESAI, MP
GUPTA, R
KARANDIKAR, ABHAY
SAXENA, K
SAMANT, V
 
Subject vlsi
cache storage
finite state machines
programmable circuits
reconfigurable architectures
telecommunication network routing
table lookup
 
Description Internet protocol (IP) address lookup is one of the major performance bottlenecks in high-end routers. This paper presents an architecture for an IP address lookup engine based on programmable finite-state machines (FSMs). The IP address lookup problem can be translated into the implementation of a large FSM. Our hardware engine is then used to implement this FSM using a structured approach, in which the large FSM is broken down into a set of smaller FSMs which are then mapped into reconfigurable hardware blocks. The design of our hardware engine is based on a regular and well structured architecture, which is easy to scale. Our simulation results demonstrate that the FSM based architecture can easily scale to wire speed performance at OC-192 rates. Unlike previous approaches, the performance of our architecture is not constrained by memory bandwidth and is, therefore, in principle scalable with very large scale integration technology.
 
Publisher IEEE
 
Date 2008-11-21T06:56:47Z
2011-11-25T12:37:47Z
2011-12-26T13:06:26Z
2011-12-27T05:54:15Z
2008-11-21T06:56:47Z
2011-11-25T12:37:47Z
2011-12-26T13:06:26Z
2011-12-27T05:54:15Z
2003
 
Type Article
 
Identifier IEEE Journal on Selected Areas in Communications 21 (4), 501-12
0733-8716
http://dx.doi.org/10.1109/JSAC.2003.810498
http://hdl.handle.net/10054/82
http://dspace.library.iitb.ac.in/xmlui/handle/10054/82
 
Language en_US