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Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

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Title Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs
 
Creator MAHAPATRA, S
BHARATH KUMAR, P
ALAM, MA
 
Subject thermodynamic stability
high temperature effects
semiconductor device models
electric potential
 
Description Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.
 
Publisher IEEE
 
Date 2008-11-24T05:24:10Z
2011-11-25T12:25:14Z
2011-12-26T13:06:56Z
2011-12-27T05:54:54Z
2008-11-24T05:24:10Z
2011-11-25T12:25:14Z
2011-12-26T13:06:56Z
2011-12-27T05:54:54Z
2004
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 51(9), 1377-79
0018-9383
http://dx.doi.org/10.1109/TED.2004.833592
http://hdl.handle.net/10054/100
http://dspace.library.iitb.ac.in/xmlui/handle/10054/100
 
Language en_US