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Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations

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Title Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations
 
Creator DESAI, MP
ANAND, B
RAMGOPAL RAO, V
 
Subject mosfet
capacitance
delay circuit
semiconductor device models
silicon-on-insulator
thick films
 
Description The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.
 
Publisher IEEE
 
Date 2008-11-21T06:57:57Z
2011-11-25T12:40:17Z
2011-12-26T13:06:59Z
2011-12-27T05:54:57Z
2008-11-21T06:57:57Z
2011-11-25T12:40:17Z
2011-12-26T13:06:59Z
2011-12-27T05:54:57Z
2004
 
Type Article
 
Identifier IEEE Electron Device Letters 25 (6), 436-38
0741-3106
http://dx.doi.org/10.1109/LED.2004.829665
http://hdl.handle.net/10054/84
http://dspace.library.iitb.ac.in/xmlui/handle/10054/84
 
Language en_US