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CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

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Title CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
 
Creator MAHAPATRA, S
MOHAPATRA, NR
NAIR, DR
RAMGOPAL RAO, V
SHUKURI, S
BUDE, JD
 
Subject monte carlo methods
voltage measurement
computer simulation
logic design
 
Description The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.
 
Publisher IEEE
 
Date 2008-11-24T05:32:32Z
2011-11-25T12:47:18Z
2011-12-26T13:08:05Z
2011-12-27T05:56:05Z
2008-11-24T05:32:32Z
2011-11-25T12:47:18Z
2011-12-26T13:08:05Z
2011-12-27T05:56:05Z
2003
 
Type Article
 
Identifier IEEE Transactions on Electron Devices 50(10), 2104-11
0018-9383
http://dx.doi.org/10.1109/TED.2003.817275
http://hdl.handle.net/10054/110
http://dspace.library.iitb.ac.in/xmlui/handle/10054/110
 
Language en_US