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A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor

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Title A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor
 
Creator WALKE, AM
VANDENBERGHE, WG
KAO, KH
VANDOOREN, A
GROESENEKEN, G
 
Subject Plackett-Burman design of experiment (PB-DOE)
process simulation of tunnel field-effect transistors (TFETs)
process variation sensitivity
TFET
FET
OPTIMIZATION
PERFORMANCE
DIODES
 
Description A process sensitivity study of a steep subthreshold swing line tunnel field-effect transistor is presented for the first time using 2-D quantum-mechanical device simulations. The impact of various process parameters on the device transfer characteristics is presented with the help of process splits. A study of the thermal budget also shows that an increase in epitaxial growth thermal budget degrades the device performance by increasing the tunneling onset voltage V-TON and the OFF-current. Through process simulation and Plackett-Burman design of experiment (PB-DOE), the epitaxial layer thickness of the channel was identified as the most critical parameter in device processing. A thickness variation from 2 to 3 nm in the highly (7 x 10(19) cm(-3)) doped epitaxial was found to cause similar to 500-mV change in the tunneling onset voltage. It was found that an increase in doping concentration in the epitaxial layer to reduce quantum confinement effects will lead to an increase in the sensitivity of the device to the thickness of the epitaxial layer. A thicker epitaxial layer (5-6 nm) with lower doping concentration is recommended for reduced epitaxial layer variation sensitivity.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-14T12:47:45Z
2014-10-14T12:47:45Z
2013
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(3)1019-1027
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2013.2242201
http://dspace.library.iitb.ac.in/jspui/handle/100/14443
 
Language en