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Effects of Small Geometries on the Performance of Gate First High-kappa Metal Gate NMOS Transistors

DSpace at IIT Bombay

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Title Effects of Small Geometries on the Performance of Gate First High-kappa Metal Gate NMOS Transistors
 
Creator WALKE, AM
MOHAPATRA, NR
 
Subject Device scaling
high-kappa dielectric
La-induced dipoles
metal gate
narrow-width effects (NWEs)
transconductance enhancement
TRENCH ISOLATION
MOSFET
RELIABILITY
OXIDE
 
Description This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the NMOS transistors increase with the decrease in the channel width, and this effect is enhanced at shorter gate lengths. PMOS transistors show conventional width dependence. The possible physicalmechanisms responsible for this anomalous behavior are identified and explained through detailed measurements. A 2-D charge-distribution-based model is proposed to model this anomalous effect. The accuracy of the proposed model is verified by comparing it with the experimental and simulated data.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-14T12:48:17Z
2014-10-14T12:48:17Z
2012
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 59(10)2582-2588
http://dx.doi.org/10.1109/TED.2012.2208647
http://dspace.library.iitb.ac.in/jspui/handle/100/14444
 
Language en