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Sub 0.5 V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices

DSpace at IIT Bombay

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Title Sub 0.5 V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices
 
Creator RAJORIYA, A
SHRIVASTAVA, M
GOSSNER, H
SCHULZ, T
RAO, VR
 
Subject Area tunneling field effect transistor (FET)
energy minimization
line tunneling FET and TFET
low voltage operation
SOC
tunnel field effect transistor
FIELD-EFFECT TRANSISTORS
GERMANIUM SOURCE
CMOS
DESIGN
 
Description Advanced mobile applications demand low power and high performance systems. In this paper, a technology computer aided design (TCAD)-based feasibility investigation of a recently proposed area tunneling field effect transistor (FET) structure is carried out from the point of high volume and ultralow power mobile applications. We demonstrate that for realization of future ultralow power and high performance systems, unique properties of area tunneling class of tunnel FET structures need to be employed. These devices are realized by engineering the tunneling region profile and tunneling cross-sectional area. The optimized devices are found to leverage up to similar to 7x energy reduction when compared with the 20-nm node MOS device options while meeting the high performance targets. Device design insights for such an area tunneling class of tunnel FET structures are discussed in this paper for the first time. It is shown that by lowering the supply voltage below 0.5 V, up to 10x reduction of the energy delay product is feasible by using area tunneling devices.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-15T12:18:13Z
2014-10-15T12:18:13Z
2013
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(8)2626-2633
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2013.2270566
http://dspace.library.iitb.ac.in/jspui/handle/100/14885
 
Language en