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The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance

DSpace at IIT Bombay

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Title The Impact of n-p-n Selector-Based Bipolar RRAM Cross-Point on Array Performance
 
Creator MANDAPATI, R
BORKAR, AS
SRINIVASAN, VSS
BAFNA, P
KARKARE, P
LODHA, S
GANGULY, U
 
Subject Bipolar Resistive RAM (RRAM)
circuit model
cross-point memory array
n-p-n selector
punch-through bipolar selector device
resistance ratio (RR)
MEMORY DEVICE
 
Description Recently, we have presented a circuit model of the n-p-n selector, validated by experimentally calibrated TCAD data and implemented in SPICE for cross-point memory array performance analysis. In this paper, we study the array circuit performance during memory operations and present five interesting insights. First, power consumption minimization during set/reset operation produces the dominant constraint that defines selector/memory pairing, and consequently the cross-point non-linearity, i.e., ON-OFF current ratio (K-I). Second, an optimal K-I exists (e. g., 104 for 1-M array size), which implies that excessively higher K-I degrades performance. Third, parallel read operation (i.e., N bits/read) can be performed and N increases with higher resistance in low-resistance state (R-LRS) without compromising read margin (RM). Fourth, higher resistance ratio improves RM. Finally, read circuit with an improved sensitivity is highly attractive as 2x lesser RM requirement can improve parallel read capability by 10x.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-15T16:45:12Z
2014-10-15T16:45:12Z
2013
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(10)3385-3392
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2013.2279553
http://dspace.library.iitb.ac.in/jspui/handle/100/15243
 
Language en