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Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx

DSpace at IIT Bombay

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Title Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx
 
Creator JOSHI, K
HUNG, S
MUKHOPADHYAY, S
SATO, T
BEVAN, M
RAJAMOHANAN, B
WEI, A
NOORI, A
MCDOUGALL, B
NI, C
LAZIK, C
SAHELI, G
LIU, P
CHU, D
DATE, L
DATTA, S
BRAND, A
SWENBERG, J
MAHAPATRA, S
 
Subject DCIV
equivalent oxide thickness (EOT) scaling
flicker noise
gate leakage
HKMG
interlayer (IL) scaling
mobility
negative-bias temperature instability (NBTI)
positive-bias temperature instability (PBTI)
 
Description The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to similar to 6 angstrom, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-16T12:25:05Z
2014-10-16T12:25:05Z
2013
 
Type Article
 
Identifier IEEE ELECTRON DEVICE LETTERS, 34(1)3-5
http://dx.doi.org/10.1109/LED.2012.2222338
http://dspace.library.iitb.ac.in/jspui/handle/100/15540
 
Language en