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A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

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Title A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects
 
Creator DAVE, M
JAIN, M
BAGHINI, MS
SHARMA, D
 
Subject Current-mode circuit
dynamic overdriving
on-chip global interconnects
process variation
HIGH-SPEED
COMMUNICATION
 
Description Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-16T14:53:55Z
2014-10-16T14:53:55Z
2013
 
Type Article
 
Identifier IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 21(2)342-353
http://dx.doi.org/10.1109/TVLSI.2012.2185835
http://dspace.library.iitb.ac.in/jspui/handle/100/15835
 
Language en