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A process and temperature compensated current reference circuit in CMOS process

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Title A process and temperature compensated current reference circuit in CMOS process
 
Creator DAVE, M
BAGHINI, MS
SHARMA, DK
 
Subject Current reference circuit
Variation
Short-channel MOSFETs
Monte Carlo simulations
 
Description A novel current reference circuit that compensates for process and temperature variations without any extra trimming is proposed in this paper. Four thousand Monte Carlo simulations show that the maximum % error (deviation from the desired value) in the reference current is +/- 5.07% considering process variations (die-to-die, wafer-to-wafer and batch-to-batch). Considering process variations and temperature change from 0 degrees C to 100 degrees C both, the maximum error in the reference current is +/- 8.56%. The proposed circuit has been fabricated in 180 nm CMOS process. Measurement results on 50 dice at room temperature show that the mean of the proposed reference current is 9.39% away from its designed value. Mean of drain current of a fixed biased MOSFET fabricated in the same run is 35.41% away from its designed value. Measurements at four different temperatures, 27 degrees C, 50 degrees C, 75 degrees C and 100 degrees C, on these dice show that the maximum error in the reference current is 17% whereas that in the drain current of a fixed biased MOSFET is 126%. In other words, the proposed current reference circuit reduces the maximum error by a factor of 7 (from 126% to 17%) when process and temperature variations both are considered without trimming. With a simple trimming circuit the maximum variation in the reference current is reduced to +/- 3.17% (C) 2011 Elsevier Ltd. All rights reserved.
 
Publisher ELSEVIER SCI LTD
 
Date 2014-10-16T14:54:25Z
2014-10-16T14:54:25Z
2012
 
Type Article
 
Identifier MICROELECTRONICS JOURNAL, 43(2)89-97
http://dx.doi.org/10.1016/j.mejo.2011.11.008
http://dspace.library.iitb.ac.in/jspui/handle/100/15836
 
Language en