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DC Compact Model for SOI Tunnel Field-Effect Transistors

DSpace at IIT Bombay

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Title DC Compact Model for SOI Tunnel Field-Effect Transistors
 
Creator BHUSHAN, B
NAYAK, K
RAO, VR
 
Subject Band-to-band (BTB) tunneling
compact model
complementary metal-oxide-semiconductor (CMOS)
low standby power (LSTP)
metal-oxide-semiconductor field-effect transistor (MOSFET)
modeling
TCAD
tunnel field-effect transistor (TFET)
Wentzel, Kramers, and Brillouin (WKB)
FET
 
Description A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage V-th, charge in the channel Q, gate capacitance C-G, drain current I-DS, subthreshold swing S, transconductance g(m), and output conductance g(DS), have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-mu m Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-10-17T04:36:32Z
2014-10-17T04:36:32Z
2012
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 59(10)2635-2642
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2012.2209180
http://dspace.library.iitb.ac.in/jspui/handle/100/15965
 
Language en