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Cascaded two-level inverter-based multilevel static VAr compensator using 12-sided polygonal voltage space vector modulation

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Title Cascaded two-level inverter-based multilevel static VAr compensator using 12-sided polygonal voltage space vector modulation
 
Creator BABU, NNVS
FERNANDES, BG
 
Subject INDUCTION-MOTOR DRIVE
UNBALANCED CONDITIONS
STAR CONFIGURATION
STATCOM CONTROL
OPERATION
ELIMINATION
PERFORMANCE
STRATEGY
 
Description A static VAr compensation scheme using 12-sided polygonal voltage space vectors for high power application is proposed in this study. Using the polygonal voltage space vectors, the dc bus utilisation is increased in linear modulation region and total harmonic distortion (THD) is improved significantly in over modulation region. The power circuit topology consists of two standard two-level inverters, which are connected in cascade through an open-ended winding transformer. In order to obtain the polygonal voltage space vectors, the dc-link voltage of inverter 2 is maintained at 0.366 times the dc-link voltage of inverter 1. A simple control strategy to maintain the required dc-link voltage ratio as well as for reactive power compensation is proposed. To verify the proposed strategy, simulation is carried in MATLAB/SIMULINK. Simulation study is performed in linear, over modulation regions of the inverter and also with unbalanced network voltages. A laboratory prototype is designed and developed to validate the simulation results. Further, this scheme is compared with a sinusoidal pulse width modulation-based VAr compensation scheme using the same topology.
 
Publisher INST ENGINEERING TECHNOLOGY-IET
 
Date 2014-10-17T05:26:47Z
2014-10-17T05:26:47Z
2012
 
Type Article
 
Identifier IET POWER ELECTRONICS, 5(8)1500-1509
http://dx.doi.org/10.1049/iet-pel.2012.0120
http://dspace.library.iitb.ac.in/jspui/handle/100/16064
 
Language en