DC Voltage Controller for Asymmetric-Twin-Converter-Topology-Based High-Power STATCOM
DSpace at IIT Bombay
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Title |
DC Voltage Controller for Asymmetric-Twin-Converter-Topology-Based High-Power STATCOM
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Creator |
ANAND, S
FERNANDES, BG CHATTERJEE, K |
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Subject |
DC voltage regulation
harmonic suppression multilevel operation pulsewidth modulation (PWM) static compensator (STATCOM) CASCADED MULTILEVEL CONVERTERS INDUSTRIAL APPLICATIONS INVERTERS MODULATION REQUIREMENTS STRATEGY |
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Description |
A four-level static compensator integrating two 2-level converters, supplying/absorbing reactive power to/from the grid, is reported in our earlier paper. Reduced component count, simpler layout for switches, and smaller dc-link capacitor values are the attractive features of the proposed topology over the diode clamped and cascaded multilevel converters. This paper suggests further improvements in this topology. Suitable selection of the dc-link voltage values reduces distortion in the current fed to the grid. In addition, circuit topology is modified to avoid the split-capacitor dc links. This reduces the number of independent dc capacitor voltages to be controlled and eliminates the flow of third-harmonic current through the transformer. In order to improve the performance, a phase-shifted carrier-based pulsewidth modulation technique is used. A mathematical model of the system is derived, based on which a controller for the scheme is designed. The effectiveness of the scheme is verified through detailed simulation study. To confirm the viability of the scheme, experimental studies are carried out on a scaled-down laboratory prototype developed for the purpose.
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Publisher |
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Date |
2014-10-17T05:41:28Z
2014-10-17T05:41:28Z 2013 |
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Type |
Article
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Identifier |
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 60(1)11-19
http://dx.doi.org/10.1109/TIE.2012.2185023 http://dspace.library.iitb.ac.in/jspui/handle/100/16093 |
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Language |
en
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