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Analog domain adaptive equalizer for low power 40 Gbps DP-QPSK receivers

DSpace at IIT Bombay

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Title Analog domain adaptive equalizer for low power 40 Gbps DP-QPSK receivers
 
Creator NAMBATH, N
MOYADE, PK
ANSARI, A
GUPTA, S
 
Subject Optical fibre communications
analog signal processing
adaptive equalizers
CMOS integrated circuits
CMOS
 
Description Electrical domain equalization of chromatic and polarization mode dispersion is attractive in coherent optical communication links. Digital coherent receivers used for this purpose are based on high speed ADCs followed by DSP, which dissipate excessive amount of power and are very costly to implement. We propose analog coherent receiver to drastically reduce the power consumption, size and cost. An adaptive feed forward equalizer for 40 Gbps dual polarization quadrature phase shift keying (DP-QPSK) systems, which processes signals in analog domain itself, is demonstrated using circuit and system simulations. The equalizer, designed in 90 nm CMOS technology, consumes 450 mW of power and occupies 1.8 mm x 1.1 mm chip area. System simulations are used to show that blind equalization is also possible when this approach is used in decision directed mode.
 
Publisher INDIAN ACAD SCIENCES
 
Date 2014-12-28T09:07:10Z
2014-12-28T09:07:10Z
2014
 
Type Article
 
Identifier SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 39(2)409-418
0256-2499
0973-7677
http://dx.doi.org/10.1007/s12046-013-0218-1
http://dspace.library.iitb.ac.in/jspui/handle/100/16246
 
Language English