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Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

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Title Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits
 
Creator NAYAK, K
BAJAJ, M
KONAR, A
OLDIGES, PJ
IWAI, H
MURALI, KVRM
RAO, VR
 
Subject SEMICONDUCTOR-DEVICE SIMULATION
SILICON NANOWIRES
PHONON TRANSPORT
BAND-STRUCTURE
ELECTRONS
PERFORMANCE
MOSFETS
HOT
 
Description In this paper, we present a fully-coupled and self-consistent continuum based three-dimensional numerical analysis to understand hot carrier and device self-heating effects for device-circuit co-optimization in Si gate-all-around nanowire FETs. We employ three-moment based energy transport formulations and two-dimensional quantum confinement effects to demonstrate negative differential conductivity in Si nanowire FETs and assess its impact on a CMOS inverter and three-stage ring oscillator. We show that strong two-dimensional quantum confinement yields volume inversion conditions in Si nanowire FETs and surround gate geometry enables better short-channel effect control. We find that hot carrier and self-heating effects can degrade ON-state current in Si nanowire FETs and severely limit the logic circuit performance due to the introduction of higher signal propagation delays. (C) 2014 The Japan Society of Applied Physics
 
Publisher IOP PUBLISHING LTD
 
Date 2014-12-28T11:26:25Z
2014-12-28T11:26:25Z
2014
 
Type Article
 
Identifier JAPANESE JOURNAL OF APPLIED PHYSICS, 53(4)
0021-4922
1347-4065
http://dx.doi.org/10.7567/JJAP.53.04EC16
http://dspace.library.iitb.ac.in/jspui/handle/100/16355
 
Language English