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Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET

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Title Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET
 
Creator WALKE, AM
VANDOOREN, A
ROOYACKERS, R
LEONELLI, D
HIKAVYY, A
LOO, R
VERHULST, AS
KAO, KH
HUYGHEBAERT, C
GROESENEKEN, G
RAO, VR
BHUWALKA, KK
HEYNS, MM
COLLAERT, N
THEAN, AVY
 
Subject Field-induced quantum confinement (FIQC)
FIQC effect
gate length and width dependence
line tunneling
TFET fabrication
TFET simulations
TFET variability
tunnel field effect transistor (TFET)
PERFORMANCE
STRAIN
 
Description This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-mu m gate length device shows ON current in excess of 20 mu A/mu m at V-GS = V-DS = 1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by similar to 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-12-28T14:14:18Z
2014-12-28T14:14:18Z
2014
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(3)707-715
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2014.2299337
http://dspace.library.iitb.ac.in/jspui/handle/100/16725
 
Language English