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Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

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Title Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology
 
Creator MITTAL, S
GUPTA, S
NAINANI, A
ABRAHAM, MC
SCHUEGRAF, K
LODHA, S
GANGULY, U
 
Subject DTMOS configuration of EDFinFET (DTEDFinFET)
epitaxially defined FinFET (EDFinFET)
FinFET
line edge roughness (LER)
V-T variability
DOPANT FLUCTUATIONS
BIPOLAR-TRANSISTORS
SIMULATION
MOSFETS
DEVICES
SILICON
GATE
TEMPERATURE
MOBILITY
DESIGN
 
Description FinFET technology is prone to suffer from line edge roughness (LER)-based V-T variation with scaling. It also lacks a simple implementation of multiple V-T technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall V-T variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher I-ON compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower I-ON than FinFET due to single gate control. However, it is capable of multiple V-T, which leads to circuit level power optimization.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-12-28T14:14:48Z
2014-12-28T14:14:48Z
2014
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(8)2711-2718
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2014.2329993
http://dspace.library.iitb.ac.in/jspui/handle/100/16726
 
Language English