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CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

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Title CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET
 
Creator NAYAK, K
BAJAJ, M
KONAR, A
OLDIGES, PJ
NATORI, K
IWAI, H
MURALI, KVRM
RAO, VR
 
Subject Circuit delays
CMOS
device performance
electrostatic integrity
gate-all-around (GAA)
logic circuits
mixed-mode (MM) simulations
quantum confinement (QC)
silicon nanowire (NW) field-effect transistor (FET)
SIMULATION
TRANSPORT
MODEL
 
Description In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-12-28T14:15:18Z
2014-12-28T14:15:18Z
2014
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(9)3066-3074
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2014.2335192
http://dspace.library.iitb.ac.in/jspui/handle/100/16727
 
Language English