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Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

DSpace at IIT Bombay

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Title Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform
 
Creator DARJI, A
AGRAWAL, S
OZA, A
SINHA, V
VERMA, A
MERCHANT, SN
CHANDORKAR, AN
 
Subject Discrete wavelet transform (DWT)
flipping structure
folded architecture
lifting scheme
parallel architecture
pipeline
EFFICIENT VLSI ARCHITECTURE
HIGH-PERFORMANCE
 
Description In this brief, an efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. This proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency. The proposed architecture is repeatable and only uses five transposition registers. The architecture can be folded to reduce the data path to only six multipliers and eight adders without affecting the critical path. The architecture implemented on a field-programmable gate-array target indicates better hardware efficiency.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2014-12-28T14:27:49Z
2014-12-28T14:27:49Z
2014
 
Type Article
 
Identifier IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 61(6)433-437
1549-7747
1558-3791
http://dx.doi.org/10.1109/TCSII.2014.2319975
http://dspace.library.iitb.ac.in/jspui/handle/100/16752
 
Language English