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SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit

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Title SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit
 
Creator PAREKH, R
BEAUVAIS, J
DROUIN, D
 
Subject Drivability
Interface
Inverter
Interconnect parasitic
Hybrid SET-CMOS circuit simulation
SET-CMOS integration
Single electron transistor (SET)
SINGLE-ELECTRON TRANSISTOR
ROOM-TEMPERATURE
DESIGN
SIMULATION
 
Description The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET-CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2(13) SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit. (C) 2014 Elsevier Ltd. All rights reserved.
 
Publisher ELSEVIER SCI LTD
 
Date 2014-12-28T17:55:29Z
2014-12-28T17:55:29Z
2014
 
Type Article
 
Identifier MICROELECTRONICS JOURNAL, 45(8)1087-1092
0026-2692
1879-2391
http://dx.doi.org/10.1016/j.mejo.2014.05.020
http://dspace.library.iitb.ac.in/jspui/handle/100/17043
 
Language English