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A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs

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Title A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs
 
Creator GOEL, N
JOSHI, K
MUKHOPADHYAY, S
NANAWARE, N
MAHAPATRA, S
 
Subject BIAS TEMPERATURE INSTABILITY
INTERFACE-TRAP GENERATION
I-DLIN TECHNIQUE
MOBILITY DEGRADATION
PHYSICAL-MECHANISM
IMPACT
SILICON
RELAXATION
PERSPECTIVE
RECOVERY
 
Description A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices. (C) 2014 Elsevier Ltd. All rights reserved.
 
Publisher PERGAMON-ELSEVIER SCIENCE LTD
 
Date 2014-12-29T05:07:01Z
2014-12-29T05:07:01Z
2014
 
Type Article
 
Identifier MICROELECTRONICS RELIABILITY, 54(3)491-519
0026-2714
http://dx.doi.org/10.1016/j.microrel.2013.12.017
http://dspace.library.iitb.ac.in/jspui/handle/100/17152
 
Language English