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Design-in-reliability: From library modeling and optimization to gate-level verification

DSpace at IIT Bombay

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Title Design-in-reliability: From library modeling and optimization to gate-level verification
 
Creator JAIN, P
PUDI, B
SREENIVASAN, M
 
Subject Reliability
NBTI
EM
Signal probability
 
Description A novel and comprehensive framework for aging analysis is presented in this work, comprehending degradation from BTI, hot-carriers and electro-migration. For the first time, all the primary variables affecting the aging of an interconnect and the transistor - namely, the equivalent duty-cycles, slews and frequencies are incorporated into the calculation. Additionally, from electro-migration stand-point, the framework allows calculation of the exact RMS and 'recovered' average current for every metal segment internal to the circuit, thus making it practically a universal model for aging analysis. Through detailed waveform-processor developed for validation, the aging model is ensured to be within 5% of exact SPICE calculations. The immediate application of such an extensive and accurate modeling is drawn in terms of influencing changes to the library design/architecture itself, showcased through circuit and layout optimization from EM, hot-carriers and NBTI constraints. Finally, we demonstrate the ultimate benefit from such a library model for doing exact gate-level aging analysis, as well as against asymmetric aging. Results from 28 nm production library models and complex SoC are shared. (C) 2014 Elsevier Ltd. All rights reserved.
 
Publisher PERGAMON-ELSEVIER SCIENCE LTD
 
Date 2014-12-29T05:08:01Z
2014-12-29T05:08:01Z
2014
 
Type Article
 
Identifier MICROELECTRONICS RELIABILITY, 54(6/7)1421-1432
0026-2714
http://dx.doi.org/10.1016/j.microrel.2014.03.001
http://dspace.library.iitb.ac.in/jspui/handle/100/17154
 
Language English