Record Details

Drift region optimization by double epitaxial layer in low and medium power rated silicon power MOSFETs

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Drift region optimization by double epitaxial layer in low and medium power rated silicon power MOSFETs
 
Creator SANDEEP, S
KOMARAGIRI, R
 
Subject SEMICONDUCTOR-DEVICES
 
Description Silicon vertically double diffused metal oxide semiconductor field effect transistor (VDMOSFET) shows a great promise for low and medium power applications and is economical when compared to their compound semiconductor counterparts. A silicon power MOSFET can be optimized using a newly proposed drift layer design strategy to increase the breakdown performance. The main difference between existing standard design and the proposed design is that, the new design uses two drift layers instead of a single drift layer with a similar process complexity. Silicon VDMOSFETs are designed and optimized through process and device simulations. The performance advantages like breakdown voltage and on current have been estimated through a combination of device and process simulations. The proposed design resulted in a significant increase in breakdown voltage from 25 to 95 V. The improvement in the breakdown voltage is attributed to reduction in the intrinsic electric field due to dopant atom re-distribution. Complete process sequence for realization of the proposed design is described. Overall system advantages gained from the implementation of newly proposed structure and process sequence in Si power devices have also been demonstrated through simulations.
 
Publisher SPRINGER
 
Date 2016-01-14T12:07:46Z
2016-01-14T12:07:46Z
2015
 
Type Article
 
Identifier JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 26(9)6692-6698
0957-4522
1573-482X
http://dx.doi.org/10.1007/s10854-015-3271-1
http://dspace.library.iitb.ac.in/jspui/handle/100/17457
 
Language en