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Analog Domain Signal Processing-Based Low-Power 100-Gb/s DP-QPSK Receiver

DSpace at IIT Bombay

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Title Analog Domain Signal Processing-Based Low-Power 100-Gb/s DP-QPSK Receiver
 
Creator NAMBATH, N
RAVEENDRANATH, RK
BANERJEE, D
SHARMA, A
SANKAR, A
GUPTA, S
 
Subject SELF-RECOVERING EQUALIZATION
DUAL-POLARIZATION QPSK
SYSTEMS
PERFORMANCE
TRANSCEIVER
DISPERSION
TRACKING
Adaptive equalizers
analog signal processing
BiCMOS integrated circuits
coherent optical receivers
Costas loop
 
Description Coherent techniques are expected to be used to meet the demand for higher data rates in short-reach optical links in the near future. Digital coherent receivers used for long haul applications are not suitable for short-reach links because of excessive power dissipation, size, and cost. The power consumption, size, and cost of the receiver can be drastically reduced by processing signals in the analog domain itself. A 100 Gb/s dual-polarization quadrature phase-shift keying receiver that uses analog domain signal processing is presented. The receiver, designed in 130-nm BiCMOS technology, consumes 3.5 W of power. Simulations show bit error rates of less than 10-3 in the presence of dispersion up to 160 ps/nm, laser linewidths of up to 200 kHz, and a frequency offset of 100 MHz between the transmitter and the receiver lasers.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2016-01-15T08:51:29Z
2016-01-15T08:51:29Z
2015
 
Type Article
 
Identifier JOURNAL OF LIGHTWAVE TECHNOLOGY, 33(15)3189-3197
0733-8724
1558-2213
http://dx.doi.org/10.1109/JLT.2015.2431732
http://dspace.library.iitb.ac.in/jspui/handle/100/18207
 
Language en