Record Details

An Experimental Perspective of Trap Generation Under BTI Stress

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title An Experimental Perspective of Trap Generation Under BTI Stress
 
Creator MUKHOPADHYAY, S
MAHAPATRA, S
 
Subject GATE STACKS
DCIV METHOD
NBTI
PBTI
Direct current IV (DCIV)
high-k metal gate (HKMG)
interlayer (IL) scaling
negative-bias temperature instability (NBTI)
positive-bias temperature instability (PBTI)
trap generation (TG)
 
Description A gated-diode or direct current IV method is used to characterize trap generation (TG) under negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) stress in different planar high-k metal gate p-channel and n-channel MOSFETs, respectively. After correction of the measurement delay, very similar time (t(STR)), voltage (V-G,V-STR), temperature (T), AC pulse duty cycle, and frequency (f) dependence of TG is seen for NBTI and PBTI. Measured TG shows power-law time dependence with a time exponent of n similar to 0.16 for NBTI and PBTI and for DC and AC stress. Uncoupled nature of voltage acceleration (Gamma) and T activation (E-A) is seen. Interlayer scaling has a similar impact on E-A and Gamma for NBTI and PBTI. However, the physical location of TG is shown to be different for NBTI and PBTI stress.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2016-01-15T09:10:07Z
2016-01-15T09:10:07Z
2015
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(7)2092-2097
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2015.2434955
http://dspace.library.iitb.ac.in/jspui/handle/100/18240
 
Language en