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Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

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Title Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness
 
Creator GUPTA, A
SHRIVASTAVA, M
BAGHINI, MS
CHANDORKAR, AN
GOSSNER, H
RAO, VR
 
Subject POWER APPLICATIONS
CMOS
device-circuit codesign
drain-extended MOS (DeMOS)
electrostatic discharge (ESD)
power amplifier (PA)
RF
shallow-trench-isolation (STI)
system-on-chip (SoC)
 
Description In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2016-01-15T09:10:37Z
2016-01-15T09:10:37Z
2015
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(10)3176-3183
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2015.2470109
http://dspace.library.iitb.ac.in/jspui/handle/100/18241
 
Language en