Record Details

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Part I: High-Voltage MOS Device Design for Improved Static and RF Performance
 
Creator GUPTA, A
SHRIVASTAVA, M
BAGHINI, MS
SHARMA, DK
GOSSNER, H
RAO, VR
 
Subject LDMOS
IMPACT
TRANSISTORS
TECHNOLOGY
Advanced CMOS
drain-extended MOS (DeMOS)
high-power RF
integrated RF power amplifier (PA)
system-on-chip (SoC)
 
Description In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.
 
Publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Date 2016-01-15T09:11:07Z
2016-01-15T09:11:07Z
2015
 
Type Article
 
Identifier IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(10)3168-3175
0018-9383
1557-9646
http://dx.doi.org/10.1109/TED.2015.2470117
http://dspace.library.iitb.ac.in/jspui/handle/100/18242
 
Language en